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Senior DFT Engineer (M/F)

Permanent contract
Salary: Not specified
A few days at home
Experience: > 7 years
Education: Master's Degree


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Job description


About SiPearl…

Founded in 2019 by Philippe Notton and financed by the European Union, SiPearl embodies Europe’s dream of mastering the technological heart of its supercomputers: the microprocessor.

SiPearl is building Rhea, the world’s first energy-efficient #HPC-dedicated microprocessor designed to work with any third-party accelerator (#GPU, #AI, #quantum). It will help Europe solving major challenges in medical research🧬, artificial intelligence, security 🛡️, energy management and climate 🌱while reducing its environmental footprint.

Since our creation in 2019, we host 170 collaborators in 6 offices: France (Maisons-Laffitte, Massy, Grenoble, Sophia Antipolis), Germany (Duisburg), Spain (Barcelona).

After a successful series A in 2023 (90M €), SiPearl has recently won an emblematic contract to equip Europe’s first exascale supercomputer, JUPITER, who will be operated by the EuroHPC’s center of research from Jülich (Germany). And as the dream of a European machine, crossing the 1 billion billion mark calculations per second thanks to an European microprocessor, is becoming reality, SiPearl is willing to hire 150 engineers by the end of 2024!


🎯 What a regular day at the job might look like:

  • Prediction of fault-models, estimation of yield and creation of innovative DfT strategies
  • Work with the system architecture team to implement the DfT concept
  • Generate ATE structural and functional test-pattern by use of RTL strobing and Gatelevel-Resimulation
  • Predict and optimize ATE test-time
  • Identify, generate and integrate the DfT IPs needed on RTL and Netlist level
  • Perform functional verification of DfT structures in RTL level
  • Perform test-specific verification and coverage analysis of DfT structures in RTL level and Netlist level
  • Work with IP design teams locally or remotely
  • Work with verification teams locally or remotely
  • Work with ASIC service company for chip implementation in different timezones


🔍 What would make you succeed in this role:

    • Graduate from an engineer school or from a Master (5 years diploma post baccalauréat)
    • A first accomplished experience of 1 year minimum, preferably in the micro electronic’s sector.
    • Drawn to this type of function, in high added value tech sectors.
    • At least 10 years knowledge in DfT concept and implementation on RTL and/or Netlist level
    • At least 10 years knowledge in Scan-Insertion (all types), MBIST, IJTAG, Boundary-Scan
    • At least 5 years of knowledge working towards ATE team
    • Experience in aligning with production-fab, understanding their yield parameters
    • Experience in split-lot and shmoo analysis and failure detection in silicon
    • Experience in RTL simulation/verification and associated environment
    • Experience in interaction with constraint development for logical synthesis
    • Experience in most of the tools: RTL compiler, Testkompress/Tetramax, Virage/Mentor, memory Bist, Mentor Bscan, Mentor SSN, Formal Equivalence tools, Nc-sim/questa-sim, revision control (git..)
    • Gained some exposure to digital ASIC front and backend design & verification processes
    • Good scripting skills, e.g. using TCL/Perl/Phyton
    • Good problem-solving capability
    • Communicate efficiently across teams
    • Good sense of independence and patient to learn and search technical information
    • Good sense of flexibility and adaptation capability/sense of initiative
    • Ability to document and train others on work developed
    • Excellent oral and writing English communication
    • autonomous and flexible
    • team-building mindset

    Recruitment process

    ✔️Discovery interview with our Talent Acquisition Partner (30’)

    ✔️ Personality test - no need to worry, there is no wrong or right answer; our goal is to get to see beyond your resume (45’)

    ✔️ Technical interview (1h)

    ✔️ Interview with your future manager (1h)


    💡 Benefits and conditions:

    • Contract: CDI
    • Benefits: meal vouchers (Sodexo), health insurance (70% covered by SiPearl), 8 to 9 RTTs, 5 days per year of remote work from any EU location
    • Work model: Hybrid (2 days remote)
    • 📍 Location: Grenoble, Barcelona, Maisons-Laffitte, Massy, Duisburg, Valbonne Sophia Antipolis
    • Awesome activities such as: Hackathons, Training Challenges, Quarterly Kick-off sessions, team events, Company events and much more


    Are you curious to learn more about us?

    At SiPearl, we are dedicated to building a diverse and inclusive workplace that thrives on the strength of varied perspectives and backgrounds. We recruit talent based on merit, experience, and alignment with our company’s goals and values.


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