Description of the Role:
In this role as an Associate Engineer (FPGA Design and Verification Engineer, Actuation Systems) actively contribute towards architectural design and RTL implementation, while supporting the full verification lifecycle, in accordance with DO-254 process.
FPGA JD:
Primary Responsibilities:
1.Develop RTL modules using VHDL for FPGA/ASIC targets, following established design guidelines.
2.Develop and maintain testbench components (drivers, monitors, scoreboards) within a UVM (Universal Verification Methodology) environment.
3.Write and execute test cases based on defined test plans to verify functional requirements.
4.Work on industry-standard protocols such as PCIe, SPI, ARINC 429, or MIL-STD-1553.
5.Collaborate with the design team to identify, debug, and resolve RTL bugs and environment issues.
6.Run simulations to collect code and functional coverage; identify and fill coverage gaps to meet project milestones.
7.Assist in the creation of verification plans and design descriptions using requirement management tools like DOORS or Jama.
8.Follow DO-254 process standards for safety-critical hardware development.

Qualifications:
• Bachelor's/Master's degree in Engineering (ECE , VLSI)
•1–3 years of industry experience in FPGA/ASIC design or verification.
•Proficiency in hardware description languages (VHDL or Verilog).
•Familiarity with simulation tools such as QuestaSim, ModelSim, or VCS.
•Foundational knowledge of SystemVerilog and the UVM framework.
•Basic scripting skills (Python, Perl, or Shell) for automation.
•Strong analytical mindset, eager to learn new protocols, and excellent communication skills for team-based problem solving.