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Firmware Engineer

CDI
Toulouse
Salaire : Non spécifié
Début : 12 août 2020
Télétravail non autorisé
Expérience : > 3 ans

Loft Orbital
Loft Orbital

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Le poste

Descriptif du poste

Role
As a member of the new R&D center in Toulouse and of the Payload Data Processing Unit (PDPU) team, you will be helping build technology that empowers our customers to process payload data onboard Loft’s satellite missions. With this ‘edge computing in space’ capability, Loft’s customers can react in real time to the data collected by their payload.

Since high flexibility and versatility play an important role, the PDPU is software-centric and supports on-ground and in-space re-programmability. Loft Orbital will be utilizing the latest technology available for the PDPU, which includes a mix of existing and next-generation component and processor technology.


Profil recherché

General Requirements

  • Scrappy and inventive: what you will be building has never been done before.
  • Prepared to be challenged and sometimes work out of your comfort zone.
  • Willingness to be accountable, autonomous, and take full ownership of projects.
  • Preferably experience with software/firmware developed for safety-critical applications or software developed for aerospace
  • Awareness and understanding of mission-critical systems and related software impact
  • A preference for agile yet process-controlled software development
  • Ability to code and document (wherever possible electronically and in-line) in a structured way
  • Ability to work both independently as well as part of a multi-disciplined team
  • Ability to learn and adopt to new technologies
  • Demonstrable history of thinking outside-the-box, without losing sight of reality
  • Experience working in both a Windows and Linux environment

Firmware Requirements

  • Understanding of space electronics and specific (technology) constraints in development and deployment
  • Extensive experience with VHDL and/or VERLOG
  • Experience in working with Rad-hard or Rad-tolerant FPGAs and SoC devices
  • Experience with SEU mitigation mechanisms
  • In-depth knowledge of development environments such as: Libero, Vivado
  • Affection with upcoming technologies for FPGA development using OpenCL / C++ / Automatic Code Generation
  • Experience with IP cores for interfacing and communication
  • Experience in structured code development incl. test benching, simulation and code coverage
  • JTAG programming / debugging
  • Preferably past experience in embedded or space hardware development

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